At KAIST Self-assembled ultra-thin silica layers for on-chip chromatography 본문 Author S. Choi, I. Park, and A. P. Pisano Conference Materials Research Society (MRS) Spring 2009 Meeting Location Apr 2009 Period San Francisco, CA, USA 목록 이전글Low-temperature, all-inorganic nanoparticle solution process for ZnO nanowire network transistor fabrication on a polymer substrate 24.12.02 다음글Nanoscale patterning and electronics on flexible substrate by direct nanoimprinting of metallic nanoparticles 24.12.02